diff options
| author | Ben Zhang <benzh@chromium.org> | 2014-12-15 17:38:11 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:10:23 +0200 |
| commit | c05710f196e2ff20881a67adace949efc29d9f1f (patch) | |
| tree | 0836558e76e677d687ebccb934609048a5c290e0 /src/mainboard/google | |
| parent | 83067610f754f89025bf781cdf8857135e946b03 (diff) | |
| download | coreboot-c05710f196e2ff20881a67adace949efc29d9f1f.tar.xz | |
samus: Add ACPI binding for rt5677 codec SPI
We'll need to find a real ACPI device ID for
the rt5677 SPI driver. "RT5677AA" is temporary.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=load firmware via SPI; hotword detection works
Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270
Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235902
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/samus/acpi/mainboard.asl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 274e8a8fca..2edc5a590a 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -345,3 +345,29 @@ Scope (\_SB.PCI0.I2C1) } } } + +Scope (\_SB.PCI0.SPI0) +{ + Device (CODC) + { + // TODO: Need official HID. + Name (_HID, "RT5677AA") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + SpiSerialBus ( + 0, // DeviceSelection (CS0?) + PolarityLow, // DeviceSelectionPolarity + FourWireMode, // WireMode + 8, // DataBitLength + ControllerInitiated, // SlaveMode + 1000000, // ConnectionSpeed (1MHz) + ClockPolarityLow, // ClockPolarity + ClockPhaseFirst, // ClockPhase + "\\_SB.PCI0.SPI0", // ResourceSource + 0, // ResourceSourceIndex + ResourceConsumer, // ResourceUsage + ) + }) + } +} |