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| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-09-27 12:05:59 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-30 12:00:57 +0000 |
| commit | 0e1245e3d065287b3f731e92fa45811225462532 (patch) | |
| tree | b24fe007196b84d3f0b3bb6b758c7e2cedaf8ca2 /src/mainboard/google | |
| parent | 7b2da05310c3cf65506946484134e8ed6400504d (diff) | |
| download | coreboot-0e1245e3d065287b3f731e92fa45811225462532.tar.xz | |
mb/google/drallion: Configure LPSS controller parameters
drallion uses below LPSS controllers:
I2C: 0/1/4
GSPI: None
UART: 0(Console)
BUG=b:141575294
Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 956e54edf9..2e8edd5b0e 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -13,6 +13,21 @@ chip soc/intel/cannonlake register "gen2_dec" = "0x00040941" # 0x940-0x947 register "gen3_dec" = "0x000c0951" # 0x950-0x95f + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "0" |