diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2018-06-20 17:04:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-26 11:33:05 +0000 |
| commit | 4c067c85507c786a661642c10583c71b80a9855c (patch) | |
| tree | c45cf396dbc01d0d29611ad0c7db9e29e60e99a6 /src/mainboard/google | |
| parent | 054516648542f8228d201ea56d8db157e4ec703f (diff) | |
| download | coreboot-4c067c85507c786a661642c10583c71b80a9855c.tar.xz | |
nocturne: configure VR per Intel recommendation
These values are Intel recommended.
IccMax = 28A
DC and AC LL = 4mOhms
Pl2 = 18w
BUG=b:79666828
BRANCH=none
TEST=Enabled p-states with patch
Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then
"emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi
image onto nocturne, boot to kernel and verify device stays alive and
responsive for several minutes without locking up.
Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27175
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 32d4f55324..235391e199 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -62,7 +62,7 @@ chip soc/intel/skylake # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl2_override" = "15" + register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" register "pch_trip_temp" = "75" @@ -87,10 +87,10 @@ chip soc/intel/skylake #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 24A | 24A | 24A | + #| IccMax | 4A | 28A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 | - #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 | + #| AcLoadline | 14.9 | 4 | 5.7 | 4.57 | + #| DcLoadline | 14.2 | 4 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, @@ -116,10 +116,10 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), + .icc_max = VR_CFG_AMP(28), .voltage_limit = 1520, - .ac_loadline = 500, - .dc_loadline = 486, + .ac_loadline = 400, + .dc_loadline = 400, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ |