diff options
| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2017-02-14 11:45:20 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-04-11 04:22:09 +0200 |
| commit | 4f4410dcbc56b14d1a078f078baab754046a5c69 (patch) | |
| tree | d24467ae6f2ef4205586e745c6da5bf02cdcb14d /src/mainboard/google | |
| parent | 08117c412c90be8647714721b7fe3109726f7ae1 (diff) | |
| download | coreboot-4f4410dcbc56b14d1a078f078baab754046a5c69.tar.xz | |
scarlet/gru: skip display because mipi driver not ready
Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.
TEST=boot to kernel on Scarlet
Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19237
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/gru/Kconfig | 5 | ||||
| -rw-r--r-- | src/mainboard/google/gru/devicetree.scarlet.cb | 20 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 43f671b600..feb14c0bcb 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -83,6 +83,11 @@ config CONSOLE_SERIAL_UART_ADDRESS ########################################################## #### Update below when adding a new derivative board. #### ########################################################## +config DEVICETREE + string + default "devicetree.scarlet.cb" if BOARD_GOOGLE_SCARLET + default "devicetree.cb" + config MAINBOARD_PART_NUMBER string default "Scarlet" if BOARD_GOOGLE_SCARLET diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb new file mode 100644 index 0000000000..2c316545f0 --- /dev/null +++ b/src/mainboard/google/gru/devicetree.scarlet.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/rockchip/rk3399 + device cpu_cluster 0 on end + register "vop_mode" = "VOP_MODE_NONE" + register "framebuffer_bits_per_pixel" = "32" +end |