diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-11-22 16:55:27 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2017-11-25 08:31:40 +0000 |
| commit | 5537f02bd59dd064ace6e06e3de473140550c9ab (patch) | |
| tree | 5591a80a74d2802c58fdf7e21f1e81a9bb31556b /src/mainboard/google | |
| parent | 6fd5a79d476b54f1670d0a06227b446ab003b2a1 (diff) | |
| download | coreboot-5537f02bd59dd064ace6e06e3de473140550c9ab.tar.xz | |
google/fizz: Disable unused i2c lines
As cr50 has now switched to using SPI, no need to enable the i2c1
anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and
I2C3.
BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many)
reboots. cat /proc/interrupts. Make sure # interrupts for 16
after booting is reasonable (not > 10k) and idma64.0,
i2c_designware.0 are not listed with that interrupt line anymore.
Should look something like this:
16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP
Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 28 |
1 files changed, 7 insertions, 21 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 73a5c5077d..df664b2e2c 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -233,17 +233,11 @@ chip soc/intel/skylake .early_init = 1, }" - # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR - # for TPM communication before memory is up. - register "i2c[1]" = "{ - .early_init = 1, - }" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, @@ -273,18 +267,10 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" - device i2c 50 on end - end - end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 off - end # I2C #3 + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R |