google/kahlee: Pass GPIO setting in amdinitenv

GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.

Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 101 insertions, 74 deletions

diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c
index 357cf10597..c65c930d08 100644
--- a/src/mainboard/google/kahlee/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/BiosCallOuts.c
@@ -19,6 +19,8 @@
 #include <soc/hudson.h>
 #include <stdlib.h>
 
+extern const GPIO_CONTROL oem_kahlee_gpio[];
+
 static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 {
 	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
@@ -26,6 +28,7 @@ static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 	if (StdHeader->Func == AMD_INIT_ENV) {
 		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
 		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+		FchParams_env->PostOemGpioTable = oem_kahlee_gpio;
 
 		/* XHCI configuration */
 		if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc
index 665e086dc7..6db037f726 100644
--- a/src/mainboard/google/kahlee/Makefile.inc
+++ b/src/mainboard/google/kahlee/Makefile.inc
@@ -17,14 +17,17 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/BiosCallOuts.c
 bootblock-y += bootblock/OemCustomize.c
 bootblock-y += ec.c
+bootblock-y += gpio.c
 
 romstage-y += BiosCallOuts.c
 romstage-y += chromeos.c
+romstage-y += gpio.c
 romstage-y += OemCustomize.c
 
 ramstage-y += BiosCallOuts.c
 ramstage-y += chromeos.c
 ramstage-y += ec.c
+ramstage-y += gpio.c
 ramstage-y += OemCustomize.c
 
 verstage-y += chromeos.c
diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
index 78b1153677..b70db1dc0e 100644
--- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
@@ -19,80 +19,7 @@
 #include <soc/hudson.h>
 #include <stdlib.h>
 
-static const GPIO_CONTROL oem_kahlee_gpio[] = {
-	/* SER TX */
-	{8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-	/* SER RX */
-	{9, Function1, FCH_GPIO_PULL_UP_ENABLE },
-
-	/* AGPIO 12 */
-	{12, Function2, FCH_GPIO_PULL_UP_ENABLE },
-
-	/* TS_EN_SOC (TouchScreen enable GPIO) */
-	{13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-
-	/* CAM_PWRON (Camera enable GPIO) */
-	{14, Function1,  FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-
-	/* EC_IN_RW */
-	{15, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-
-	/* APU_I2C_3_SCL */
-	{19, Function1, FCH_GPIO_PULL_UP_ENABLE },
-
-	/* APU_I2C_3_SDA */
-	{20, Function1, FCH_GPIO_PULL_UP_ENABLE },
-
-
-	/* APU_BT_ON# */
-	{24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-
-	/* DEVSLP1_SSD */
-	{67, Function1, FCH_GPIO_PULL_UP_ENABLE},
-
-	/* DEVSLP1_EMMC */
-	/* No Connect for now.
-	 * {70, Function1, FCH_GPIO_PULL_UP_ENABLE},
-	 */
-
-	/* SPI_TPM_CS_L */
-	{76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						  | FCH_GPIO_OUTPUT_ENABLE},
-
-	/* CAM_LED# */
-	{84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-
-	/* TS_RST#  (TouchScreen Reset) */
-	{85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						| FCH_GPIO_OUTPUT_ENABLE},
-
-	/* WLAN_RST#_AUX */
-	{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
-						 | FCH_GPIO_OUTPUT_ENABLE},
-
-	/* BD_ID1 */
-	{135, Function1, 0 },
-
-	/* TPM_SERIRQ# */
-	{139, Function1, FCH_GPIO_PULL_UP_ENABLE },
-
-	/* BD_ID2 */
-	{140, Function1, 0 },
-
-	/* APU_SPI_WP */
-	{142, Function1, FCH_GPIO_PULL_UP_ENABLE },
-
-	/* BD_ID3 */
-	{144, Function1, 0 },
-
-	{-1}
-};
+extern const GPIO_CONTROL oem_kahlee_gpio[];
 
 static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
 {
diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c
new file mode 100644
index 0000000000..56a5e3d2c7
--- /dev/null
+++ b/src/mainboard/google/kahlee/gpio.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <FchPlatform.h>
+#include <soc/hudson.h>
+#include <stdlib.h>
+
+const GPIO_CONTROL oem_kahlee_gpio[] = {
+	/* SER TX */
+	{8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* SER RX */
+	{9, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* AGPIO 12 */
+	{12, Function2, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* TS_EN_SOC (TouchScreen enable GPIO) */
+	{13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* CAM_PWRON (Camera enable GPIO) */
+	{14, Function1,  FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* EC_IN_RW */
+	{15, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* APU_I2C_3_SCL */
+	{19, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* APU_I2C_3_SDA */
+	{20, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+
+	/* APU_BT_ON# */
+	{24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* DEVSLP1_SSD */
+	{67, Function1, FCH_GPIO_PULL_UP_ENABLE},
+
+	/* DEVSLP1_EMMC */
+	/* No Connect for now.
+	 * {70, Function1, FCH_GPIO_PULL_UP_ENABLE},
+	 */
+
+	/* SPI_TPM_CS_L */
+	{76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						  | FCH_GPIO_OUTPUT_ENABLE},
+
+	/* CAM_LED# */
+	{84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* TS_RST#  (TouchScreen Reset) */
+	{85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* WLAN_RST#_AUX */
+	{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						 | FCH_GPIO_OUTPUT_ENABLE},
+
+	/* BD_ID1 */
+	{135, Function1, 0 },
+
+	/* TPM_SERIRQ# */
+	{139, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* BD_ID2 */
+	{140, Function1, 0 },
+
+	/* APU_SPI_WP */
+	{142, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* BD_ID3 */
+	{144, Function1, 0 },
+
+	{-1}
+};