diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-01 17:11:31 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-25 22:31:31 +0100 |
| commit | 654d8051d48aa9c735edf2bbdaf097506ce47d2f (patch) | |
| tree | 4e1816db80b4f1c8b3a4eb8bc2a180fd48cf6124 /src/mainboard/google | |
| parent | 29a321dc9706b04f6ca2507a25a5dd85e32f79ac (diff) | |
| download | coreboot-654d8051d48aa9c735edf2bbdaf097506ce47d2f.tar.xz | |
ryu: switch to padconfig API in romstage
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built.
Change-Id: I84abb36d4b39b60837b68c24f5cacffb74c1a985
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42a5d3a8a8c46b20361522bc5cb1c1faafaae0cc
Original-Change-Id: Ib3ee8a14a34d0a2e73f3b912879eb65ac2d97c50
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210900
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rush_ryu/romstage.c | 64 |
1 files changed, 25 insertions, 39 deletions
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index 4ebb8edf24..3234252f0a 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -19,59 +19,45 @@ #include <soc/addressmap.h> #include <soc/clock.h> +#include <soc/padconfig.h> #include <soc/nvidia/tegra/i2c.h> -#include <soc/nvidia/tegra132/pinmux.h> -#include <soc/nvidia/tegra132/gpio.h> #include <soc/romstage.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; -static void configure_tpm_i2c_bus(void) -{ - clock_configure_i2c_scl_freq(i2c3, PLLP, 19); - i2c_init(2); -} +static const struct pad_config padcfgs[] = { + /* AP_SYS_RESET_L */ + PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP), + /* TPM on I2C3 */ + PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3), + PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3), + /* EC on I2C2 */ + PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_INPUT_ENABLE, I2C2), + PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_INPUT_ENABLE, I2C2), +}; -static void configure_ec_i2c_bus(void) -{ - clock_configure_i2c_scl_freq(i2c2, PLLP, 100); - i2c_init(1); -} - -static void mainboard_init_tpm_i2c(void) +static void configure_clocks(void) { + /* TPM on I2C3 */ clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0); + clock_configure_i2c_scl_freq(i2c3, PLLP, 19); - gpio_output(GPIO(I5), 1); - - /* I2C3 (cam) clock */ - pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, - PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - /* I2C3 (cam) data */ - pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, - PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - - configure_tpm_i2c_bus(); -} - -static void mainboard_init_ec_i2c(void) -{ + /* EC on I2C2 */ clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0); - - /* I2C2 (GEN2) clock */ - pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, - PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); - /* I2C2 (GEN2) data */ - pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, - PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); - - configure_ec_i2c_bus(); + clock_configure_i2c_scl_freq(i2c2, PLLP, 100); } void romstage_mainboard_init(void) { - mainboard_init_tpm_i2c(); - mainboard_init_ec_i2c(); + configure_clocks(); + + /* Bring up controller interfaces for ramstage loading. */ + soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); + + /* TPM */ + i2c_init(2); + /* EC */ + i2c_init(1); } void mainboard_configure_pmc(void) |