diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-11-01 13:35:32 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-03-11 19:55:58 +0100 |
| commit | 714b1e8b6ca00f43f920e7a3f3db8f039356ce50 (patch) | |
| tree | ec5b75dc6a7880d499780be0e5e4241baa6eb901 /src/mainboard/google | |
| parent | 3c9f17462a618d4fc848fac852a0f2bfca50c8d3 (diff) | |
| download | coreboot-714b1e8b6ca00f43f920e7a3f3db8f039356ce50.tar.xz | |
rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.
This is hopefully just temporary until the issues with XHCI
can be worked out.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi
Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rambi/devicetree.cb | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 66d98edf24..af115a6cbc 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -5,6 +5,24 @@ chip soc/intel/baytrail register "sata_ahci" = "0x1" register "ide_legacy_combined" = "0x0" + # Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Rambi board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + device cpu_cluster 0 on device lapic 0 on end end |