Falco/Slippy: Patch to refactor haswell/gma.c and mainboard/google/slippy/i915io.c

A large portion of documented registers have been initialized using macros. Only a few
undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant
calls. However, some more work is required to correctly identify which calls are not required.

All the io_writes are replaced by gtt_writes.

Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66204
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6600
Tested-by: build bot (Jenkins)

2 files changed, 101 insertions, 174 deletions

diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 4b002ecddf..7c95e40667 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -87,33 +87,13 @@
 
 static unsigned int *mmio;
 static unsigned int graphics;
-static unsigned short addrport;
-static unsigned short dataport;
 static unsigned int physbase;
 
-static int ioread = 0, iowrite = 0;
-
 void ug1(int);
 void ug2(int);
 void ug22(int);
 void ug3(int);
 
-unsigned long io_i915_read32(unsigned long addr)
-{
-	unsigned long val;
-	outl(addr, addrport);
-	val = inl(dataport);
-	ioread += 2;
-	return val;
-}
-
-void io_i915_write32(unsigned long val, unsigned long addr)
-{
-	outl(addr, addrport);
-	outl(val, dataport);
-	iowrite += 2;
-}
-
 /* GTT is the Global Translation Table for the graphics pipeline.
  * It is used to translate graphics addresses to physical
  * memory addresses. As in the CPU, GTTs map 4K pages.
@@ -133,6 +113,8 @@ void io_i915_write32(unsigned long val, unsigned long addr)
  * starting at physbase.
  */
 
+#define GTT_PTE_BASE (2 << 20)
+
 static void
 setgtt(int start, int end, unsigned long base, int inc)
 {
@@ -144,7 +126,8 @@ setgtt(int start, int end, unsigned long base, int inc)
 		 * the values that mrc does no
 		 * useful setup before we run this.
 		 */
-		io_i915_write32(word|1,(i*4)|1);
+		gtt_write(GTT_PTE_BASE + i * 4, word|1);
+		gtt_read(GTT_PTE_BASE + i * 4);
 	}
 }
 
@@ -157,7 +140,7 @@ static void palette(void)
 	unsigned long color = 0;
 
 	for(i = 0; i < 256; i++, color += 0x010101){
-		io_i915_write32(color, _LGC_PALETTE_A + (i<<2));
+		gtt_write(_LGC_PALETTE_A + (i<<2),color);
 	}
 }
 
@@ -251,8 +234,8 @@ void mainboard_train_link(struct intel_dp *intel_dp)
 	u8 read_val;
 	u8 link_status[DP_LINK_STATUS_SIZE];
 
-	io_i915_write32(0x80040000,DP_TP_CTL_A);
-	io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011,DP_A);
+	gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+	gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011);
 
 	intel_dp_get_training_pattern(intel_dp, &read_val);
 	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
@@ -260,7 +243,7 @@ void mainboard_train_link(struct intel_dp *intel_dp)
 	intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
 	intel_dp_get_link_status(intel_dp, link_status);
 
-	io_i915_write32(0x80040100,DP_TP_CTL_A);
+	gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
 
 	intel_dp_get_training_pattern(intel_dp, &read_val);
 	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
@@ -270,34 +253,54 @@ void mainboard_train_link(struct intel_dp *intel_dp)
 	intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
 }
 
-int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
-		unsigned int gfx, unsigned int init_fb);
-int i915lightup(unsigned int pphysbase, unsigned int piobase,
-		unsigned int pmmio, unsigned int pgfx, unsigned int init_fb)
+#define TEST_GFX 0
+
+#if TEST_GFX
+static void test_gfx(struct intel_dp *dp)
+{
+	int i;
+
+	/* This is a sanity test code which fills the screen with two bands --
+	   green and blue. It is very useful to ensure all the initializations
+	   are made right. Thus, to be used only for testing, not otherwise
+	*/
+	for (i = 0; i < (dp->edid.va - 4); i++) {
+		u32 *l;
+		int j;
+		u32 tcolor = 0x0ff;
+		for (j = 0; j < (dp->edid.ha-4); j++) {
+			if (j == (dp->edid.ha/2)) {
+				tcolor = 0xff00;
+			}
+			l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+			memcpy(l,&tcolor,sizeof(tcolor));
+		}
+	}
+}
+#else
+static void test_gfx(struct intel_dp *dp) {}
+#endif
+
+int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+		unsigned int pgfx, unsigned int init_fb)
 {
 	int must_cycle_power = 0;
 	struct intel_dp adp, *dp = &adp;
-	/* frame buffer pointer */
-	/* u32 *l; */
 	int i;
 	int edid_ok;
-	/* u32 tcolor = 0xff; */
 	int pixels = FRAME_BUFFER_BYTES/64;
 
 	mmio = (void *)pmmio;
-	addrport = piobase;
-	dataport = addrport + 4;
 	physbase = pphysbase;
 	graphics = pgfx;
 	printk(BIOS_SPEW,
 	       "i915lightup: graphics %p mmio %p"
-	       "addrport %04x physbase %08x\n",
-	       (void *)graphics, mmio, addrport, physbase);
+	       "physbase %08x\n",
+	       (void *)graphics, mmio, physbase);
 
 	void runio(struct intel_dp *dp);
 	void runlinux(struct intel_dp *dp);
-
-	dp->gen = 8; // ??
+	dp->gen = 8; // This is gen 8 which we believe is Haswell
 	dp->is_haswell = 1;
 	dp->DP = 0x2;
 	/* These values are used for training the link */
@@ -308,6 +311,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
 	dp->panel_power_cycle_delay = 600;
 	dp->pipe = PIPE_A;
 	dp->port = PORT_A;
+	dp->plane = PLANE_A;
 	dp->clock = 160000;
 	dp->bpp = 32;
 	dp->type = INTEL_OUTPUT_EDP;
@@ -327,8 +331,6 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
                 memset((void*)graphics, 0, 4096);
         }
 
-	//intel_prepare_ddi_buffers(0, 0);
-	//ironlake_edp_panel_vdd_on(dp);
 	dp->address = 0x50;
 
 	if ( !intel_dp_get_dpcd(dp) )
@@ -351,9 +353,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
 
 	dp_init_dim_regs(dp);
 
-	/* more undocumented stuff. */
-	/* possibly not even needed. */
-	io_i915_write32(0x00000021,0x6f410);
+	intel_ddi_set_pipe_settings(dp);
 
 	runio(dp);
 
@@ -362,31 +362,19 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
 	pixels = dp->edid.ha * (dp->edid.va-4) * 4;
 	printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
 
-	/* for (i = 0; i < (dp->edid.va - 4); i++) { */
-	/* 	int j; */
-	/* 	tcolor = 0x0ff; */
-	/* 	for (j = 0; j < (dp->edid.ha-4); j++) { */
-	/* 		if (j == (dp->edid.ha/2)) { */
-	/* 			tcolor = 0xff00; */
-	/* 		} */
-	/* 		l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); */
-	/* 		memcpy(l,&tcolor,sizeof(tcolor)); */
-	/* 	} */
-	/* }	 */
+	test_gfx(dp);
 
 	set_vbe_mode_info_valid(&dp->edid, graphics);
 	i915_init_done = 1;
-	//io_i915_write32( 0x80000000,BLC_PWM_CPU_CTL2);
-	//io_i915_write32( 0x80000000,BLC_PWM_PCH_CTL1);
 	return i915_init_done;
 
 fail:
 	printk(BIOS_SPEW, "Graphics could not be started;");
 	if (0 && must_cycle_power){
 		printk(BIOS_SPEW, "Turn off power and wait ...");
-		io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
+		gtt_write(PCH_PP_CONTROL,0xabcd0000);
 		udelay(600000);
-		io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
+		gtt_write(PCH_PP_CONTROL,0xabcd000f);
 	}
 	printk(BIOS_SPEW, "Returning.\n");
 	return 0;
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index 0801122355..7fbffb6616 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -47,34 +47,17 @@ void runio(struct intel_dp *dp)
 	/* vbios spins at this point. Some haswell weirdness? */
 	intel_dp_wait_panel_power_control(0xabcd0008);
 
-	/* This is stuff we don't totally understand yet. */
-	io_i915_write32(0x03a903a9,BLC_PWM_CPU_CTL);
-	io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2);
-	io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1);
-	io_i915_write32(0x00ffffff,0x64ea8);
-	io_i915_write32(0x00040006,0x64eac);
-	io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
-	io_i915_write32(0x80000000,0x45400);
-	intel_dp_wait_reg(0x00045400, 0xc0000000);
-	io_i915_write32(0x8000298e,CPU_VGACNTRL);
-	io_i915_write32(0x00000000,_CURACNTR);
-	io_i915_write32(0x00000000,_CURABASE);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32(0x00000000,_CURBCNTR_IVB);
-	io_i915_write32(0x00000000,_CURBBASE_IVB);
-	io_i915_write32(0x00000000,_DSPBCNTR);
-	io_i915_write32(0x00000000,_DSPBSURF);
-	io_i915_write32(0x00000000,0x72080);
-	io_i915_write32(0x00000000,0x72084);
-	io_i915_write32(0x00000000,_DVSACNTR);
-	io_i915_write32(0x00000000,_DVSASURF);
-	io_i915_write32(0x00008000,DEIIR);
-	intel_dp_wait_reg(0x00044008, 0x00000000);
-	io_i915_write32(0x8020298e,CPU_VGACNTRL);
-	io_i915_write32(/*0x00000800*/dp->stride,_DSPASTRIDE);
-	io_i915_write32(0x00000000,_DSPAADDR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
+	/* This should be a function like intel_panel_enable_backlight
+	   However, we are not sure how the value 0x3a9 comes up.
+	   It has to do something with PWM frequency */
+	gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+	gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+	gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
+
+	gtt_write(DEIIR,0x00008000);
+	intel_dp_wait_reg(DEIIR, 0x00000000);
+
+	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
 
 	intel_dp_sink_dpms(dp, 0);
 
@@ -83,25 +66,18 @@ void runio(struct intel_dp *dp)
 	intel_dp_set_m_n_regs(dp);
 
 	intel_dp_set_resolution(dp);
-	io_i915_write32(dp->pipesrc,PIPESRC(dp->pipe));
-	io_i915_write32(0x00000000, PIPECONF(dp->transcoder));
-	io_i915_write32(0x00000000, PCH_TRANSCONF(dp->pipe));
-
-	io_i915_write32(0x20000000,PORT_CLK_SEL_A);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x14000000,_DSPACNTR);
-	io_i915_write32(dp->stride,_DSPASTRIDE);
-
-	io_i915_write32(0x00000000,_DSPAADDR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32(0x00000080,DEIIR);
-
-	io_i915_write32(0x00230000,TRANS_DDI_FUNC_CTL_EDP);
-	io_i915_write32(0x00000010,0x7f008);
-	io_i915_write32(dp->flags,TRANS_DDI_FUNC_CTL_EDP);
-	io_i915_write32(0x80000010,0x7f008);
+
+	gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+	gtt_write(PIPECONF(dp->transcoder),0x00000000);
+	gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
+
+	gtt_write(PORT_CLK_SEL(dp->port),PORT_CLK_SEL_LCPLL_1350);
+	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+	gtt_write(DEIIR,0x00000080);
+
+	gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
+	gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
 
 	intel_dp_wait_panel_power_control(0xabcd000a);
 
@@ -114,14 +90,13 @@ void runio(struct intel_dp *dp)
 	intel_dp_i2c_read(dp, &read_val);
 
 	/* this needs to be a call to a function */
-	io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091,DP_A);
-	io_i915_write32(0x00000001,TRANS_DDI_FUNC_CTL_EDP+0x10);
-	io_i915_write32(0x80040011,DP_TP_CTL_A);
-	io_i915_write32( DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091,DP_A);
+	gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
+	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+	gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
 
 	/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
-	io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a,PCH_PP_ON_DELAYS);
-	io_i915_write32( PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a,PCH_PP_ON_DELAYS);
+	gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
+	gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
 
 	intel_dp_set_bw(dp);
 	intel_dp_set_lane_count(dp);
@@ -129,69 +104,33 @@ void runio(struct intel_dp *dp)
 	mainboard_train_link(dp);
 
 	/* need a function: intel_ddi_set_tp or similar */
-	io_i915_write32(0x80040200,DP_TP_CTL_A);
-	io_i915_write32(0x80040300,DP_TP_CTL_A);
-	io_i915_write32(0x03a903a9,BLC_PWM_CPU_CTL);
-	io_i915_write32(0x03a903a9,BLC_PWM_PCH_CTL2);
-	io_i915_write32(0x80000000,BLC_PWM_PCH_CTL1);
+	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
+	gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+	gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+	gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+	gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
 
 	/* some of this is not needed. */
-	io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
-	io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
-	io_i915_write32(0x00000000,SDEIIR);
-	io_i915_write32(0x00000000,SDEIIR);
-	io_i915_write32(0x00000000,DEIIR);
-	io_i915_write32(0x80000000,0x45400);
-	intel_dp_wait_reg(0x00045400, 0xc0000000);
-	io_i915_write32(0x80000000,0x45400);
-	intel_dp_wait_reg(0x00045400, 0xc0000000);
-	printk(BIOS_SPEW, "pci dev(0x0,0x2,0x0,0x6)");
-	io_i915_write32(0x80000000,0x45400);
-	intel_dp_wait_reg(0x00045400, 0xc0000000);
-	io_i915_write32(0x8000298e,CPU_VGACNTRL);
-	io_i915_write32(0x00000000,_CURACNTR);
-	io_i915_write32(0x00000000,_CURABASE);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32(0x00000000,_CURBCNTR_IVB);
-	io_i915_write32(0x00000000,_CURBBASE_IVB);
-	io_i915_write32(0x00000000,_DSPBCNTR);
-	io_i915_write32(0x00000000,_DSPBSURF);
-	io_i915_write32(0x00000000,0x72080);
-	io_i915_write32(0x00000000,0x72084);
-	io_i915_write32(0x00000000,_DVSACNTR);
-	io_i915_write32(0x00000000,_DVSASURF);
-	io_i915_write32(0x00008000,DEIIR);
-	intel_dp_wait_reg(0x00044008, 0x00000000);
-
-	/* we just turned vdd off. We're not going to wait. The panel is up. */
-	io_i915_write32(0x8020298e,CPU_VGACNTRL);
-	io_i915_write32(/*0x00000640*/dp->stride,_DSPASTRIDE);
-	io_i915_write32(0x00000000,_DSPAADDR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x00000000,_DSPACNTR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	/* io_i915_write32(dp->pfa_pos,_PFA_WIN_POS); */
-	/* io_i915_write32(0x00000000,_PFA_WIN_SZ); */
-	io_i915_write32(dp->pipesrc,_PIPEASRC);
-	/* io_i915_write32(dp->pfa_pos,_PFA_WIN_POS); */
-	/* io_i915_write32(dp->pfa_ctl,_PFA_CTL_1); */
-	/* io_i915_write32(dp->pfa_sz,_PFA_WIN_SZ); */
-	io_i915_write32(0x00000080,DEIIR);
-	intel_dp_wait_reg(0x00044008, 0x00000000);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x14000000,_DSPACNTR);
-	io_i915_write32(/*0x00000640*/dp->stride,_DSPASTRIDE);
-	io_i915_write32(0x00000000,_DSPAADDR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x94000000,_DSPACNTR);
-	io_i915_write32((/* DISPPLANE_SEL_PIPE(0=A,1=B) */0x0<<24)|0x98000000,_DSPACNTR);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-
-	io_i915_write32( EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON |0x00000007,PCH_PP_CONTROL);
-
-	io_i915_write32( PORTD_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |0x10100010,SDEISR+0x30);
-	io_i915_write32( DIGITAL_PORTA_HOTPLUG_ENABLE |0x00000010,DIGITAL_PORT_HOTPLUG_CNTRL);
-	io_i915_write32(0x00000000,SDEIIR);
-	io_i915_write32(0x00000000,SDEIIR);
-	io_i915_write32(0x00000000,DEIIR);
+	gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
+
+	gtt_write(SDEIIR,0x00000000);
+	gtt_write(DEIIR,0x00000000);
+	gtt_write(DEIIR,0x00008000);
+	intel_dp_wait_reg(DEIIR, 0x00000000);
+
+	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+	gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+
+	gtt_write(DEIIR,0x00000080);
+	intel_dp_wait_reg(DEIIR, 0x00000000);
+
+	gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+	gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+
+	gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
+
+	gtt_write(SDEIIR,0x00000000);
+	gtt_write(SDEIIR,0x00000000);
+	gtt_write(DEIIR,0x00000000);
 }