diff options
| author | Martin Roth <martinroth@chromium.org> | 2018-03-06 14:42:41 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-09 12:41:24 +0000 |
| commit | 7b37668650f8ee13ace646dc98584074992a696f (patch) | |
| tree | fa7f77f49ecae10cbe6424212697f2a06ad43d3e /src/mainboard/google | |
| parent | 001848c415c0cd72c7d9961897d53fb2efbceca0 (diff) | |
| download | coreboot-7b37668650f8ee13ace646dc98584074992a696f.tar.xz | |
mainboard/google/kahlee: Set GPIO 40 to input
GPIO 40 isn't currently being used, so set it to be an input.
BUG=b:73387647
TEST=Build & boot grunt
Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index de70be40d3..cab7611fc9 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -83,8 +83,8 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* GPIO_40 - EMMC_BRIDGE_RST_L */ - PAD_GPO(GPIO_40, HIGH), + /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */ + PAD_GPI(GPIO_40, PULL_UP), /* GPIO_42 - S5_MUX_CTRL */ PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE), |