diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2019-01-28 13:32:31 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-30 11:03:27 +0000 |
| commit | ab92f26a13f4656821f9dff93f180cb1a33c1c3e (patch) | |
| tree | 09fab379bff46802e1130bb3b63ff8c9646ac959 /src/mainboard/google | |
| parent | 168f046d71ae8ec3ffc2c180a71ba2fde852f1e2 (diff) | |
| download | coreboot-ab92f26a13f4656821f9dff93f180cb1a33c1c3e.tar.xz | |
mainboard/{google,intel}: Remove SaGv hard coding
Remove hard coding for SaGv config in devicetree.cb and apply macro for
SaGv config for CNL variants boards
Change-Id: If007589d5c1368602928b1550ec8788e65f70c05
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f9d458208d..4efaf55191 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/cannonlake register "gen3_dec" = "0x000c0951" # 0x950-0x95f # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 0bf7e984a6..85d4f9def9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/cannonlake register "gen3_dec" = "0x000c0951" # 0x950-0x95f # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" |