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author | Roy Mingi Park <roy.mingi.park@intel.com> | 2019-04-12 21:29:14 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-23 10:10:19 +0000 |
commit | ba851170fba9157b45bfdc74fe60873c187cac96 (patch) | |
tree | 384590ffbc2351e527f8528aef7a292bb1f23149 /src/mainboard/google | |
parent | e98a7518234978ab0efbe7868f7c172302033757 (diff) | |
download | coreboot-ba851170fba9157b45bfdc74fe60873c187cac96.tar.xz |
mb/google/sarein: Add power control for Arcada touchscreen
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.
BUG=b:129899315
TEST= Measure touchscreen power from Arcada during S0iX
Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/sarien/variants/arcada/devicetree.cb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 2056dd6280..57c4e65e70 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -302,8 +302,10 @@ chip soc/intel/cannonlake register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" |