diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-02-26 14:49:00 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-09 21:40:32 +0000 |
| commit | efbfdd2d60043b75d87f4149f28eceafa19643d8 (patch) | |
| tree | dff39e2cfd8e905f343d1d1f4e64e16c2526aac7 /src/mainboard/google | |
| parent | d83faceefa77e9a769a7e6de4ad5313d5afc422a (diff) | |
| download | coreboot-efbfdd2d60043b75d87f4149f28eceafa19643d8.tar.xz | |
soc/intel/skylake: Move PCR DMI programming into bootblock
As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit
[15:0] to the same value program in LPC PCI offset 82h. Also this
cycle decoding is only allowed to set when SRLOCK is not set.
Hence move the required programming from lpc.c to pch.c.
Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO
Kconfig is selected.
Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
0 files changed, 0 insertions, 0 deletions