diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-11-15 11:40:58 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-06 21:56:20 +0100 |
| commit | f00af5833abd0792429ffb28c551eedb7b59aafc (patch) | |
| tree | 0d96a364fbd32266d7df1c279dda9fb7b89222d6 /src/mainboard/google | |
| parent | c49782cbe7a79cca03c3c20c647211367bb0a03e (diff) | |
| download | coreboot-f00af5833abd0792429ffb28c551eedb7b59aafc.tar.xz | |
rockchip/rk3399: sdram: use register to calculate sdram sizes
We may support different sdram sizes on one board in future, so
we need to calculate sdram sizes from sdram drvier.
BRANCH=None
BUG=None
TEST=boot kevin
Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e
Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411600
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/gru/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/google/gru/romstage.c | 6 |
2 files changed, 2 insertions, 8 deletions
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 57b1762578..f07bc82320 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -60,10 +60,6 @@ config MAINBOARD_VENDOR string default "Google" -config DRAM_SIZE_MB - int - default 4096 - config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x5 diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 55ed79a574..7f84a2a2a1 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -33,9 +33,6 @@ #include "pwm_regulator.h" -static const uint64_t dram_size = - (uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS); - static void init_dvs_outputs(void) { pwm_regulator_configure(PWM_REGULATOR_GPU, 900); @@ -66,7 +63,8 @@ void main(void) sdram_init(get_sdram_config()); - mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); + mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB, + CACHED_MEM); mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); cbmem_initialize_empty(); run_ramstage(); |