diff options
| author | Furquan Shaikh <furquan@google.com> | 2019-02-12 08:15:47 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-02-13 18:46:39 +0000 |
| commit | 32bc1dc531712e187f830d84e6b03e8b8f5ed936 (patch) | |
| tree | aae6e8a9f4adb2a420d91dcc4891596402a095eb /src/mainboard/google | |
| parent | 883d8215038ccd783bed03b9acf175ec5f55d062 (diff) | |
| download | coreboot-32bc1dc531712e187f830d84e6b03e8b8f5ed936.tar.xz | |
mb/google/hatch: Bump up the BIOS region to 28MiB
This change bumps up the BIOS region to 28MiB to use the hole
between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only
the top 16MiB actually gets memory mapped. Thus, the change ensures
that only RW_LEGACY lies in the 12MiB that is not memory mapped.
BUG=b:123443737
TEST=Verified that hatch still boots up. Ensured that fmap dump looks
correct.
Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/hatch/chromeos.fmd | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 25d579b66d..e0007937d3 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -3,34 +3,37 @@ FLASH@0xfe000000 0x2000000 { SI_DESC@0x0 0x1000 SI_ME@0x1000 0x3ff000 } - SI_BIOS@0x1400000 0xC00000 { - RW_SECTION_A@0x0 0x2d0000 { + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 } - RW_SECTION_B@0x2d0000 0x2d0000 { + RW_SECTION_B@0x13e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { + RW_ELOG@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 + RW_VPD@0x38000 0x2000 + RW_NVRAM@0x3a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor # memory protected range specification. - WP_RO@0x800000 0x400000 { + WP_RO@0x1800000 0x400000 { RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 |