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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-04-23 13:52:54 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-04-28 16:46:00 +0000
commit5b574e1c859a095ecdf2728a1a6db2d854bbb668 (patch)
treebfe8e0d52cbd2b1fc8f41d2e8935a97391f3889e /src/mainboard/google
parentc486c78020fc426d8ddb2a74fac5f7c402e4af29 (diff)
downloadcoreboot-5b574e1c859a095ecdf2728a1a6db2d854bbb668.tar.xz
mb/google/deltaur: Change H1 I2C speed to STANDARD
Currently, Deltaur’s I2C speed has not been tuned yet, so slow down the H1 I2C to avoid I2C error for short term. Error logs: Reading cr50 TPM mode I2C receive timeout I2C read failed: bus 3 addr 0x50 BUG=b:154310066 TEST=Check H1 has no I2C error occurring and can be updated by gsctool. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index e0b3d500d9..498266efdd 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -92,7 +92,7 @@ chip soc/intel/tigerlake
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
- .speed = I2C_SPEED_FAST,
+ .speed = I2C_SPEED_STANDARD,
.early_init = 1,
},
.i2c[5] = {