diff options
author | Aaron Durbin <adurbin@chromium.org> | 2016-01-25 17:02:11 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-04 17:40:44 +0100 |
commit | 849e4f5e786859668711ef3560aad23fa4d06124 (patch) | |
tree | 320605592c6932611bf5a7aa437dc8557bed78bd /src/mainboard/google | |
parent | 5e29106ee448f9a96cae7e96323cd0cd6b7e7f30 (diff) | |
download | coreboot-849e4f5e786859668711ef3560aad23fa4d06124.tar.xz |
google/chell: perform early init for CAR *stage
In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built chell w/ separate verstage and booted.
Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5
Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324072
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13582
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/chell/Makefile.inc | 3 | ||||
-rw-r--r-- | src/mainboard/google/chell/car.c | 35 | ||||
-rw-r--r-- | src/mainboard/google/chell/romstage.c | 17 |
3 files changed, 38 insertions, 17 deletions
diff --git a/src/mainboard/google/chell/Makefile.inc b/src/mainboard/google/chell/Makefile.inc index 22e770b7f4..c0ca567339 100644 --- a/src/mainboard/google/chell/Makefile.inc +++ b/src/mainboard/google/chell/Makefile.inc @@ -16,6 +16,7 @@ subdirs-y += spd romstage-y += boardid.c +romstage-y += car.c romstage-y += pei_data.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -30,3 +31,5 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +verstage-y += car.c diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/google/chell/car.c new file mode 100644 index 0000000000..7791b92980 --- /dev/null +++ b/src/mainboard/google/chell/car.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <fsp/car.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void car_mainboard_post_console_init(void) +{ + /* Ensure the EC and PD are in the right mode for recovery */ + google_chromeec_early_init(); + + early_config_gpio(); +} diff --git a/src/mainboard/google/chell/romstage.c b/src/mainboard/google/chell/romstage.c index f06934f57f..65c095dd65 100644 --- a/src/mainboard/google/chell/romstage.c +++ b/src/mainboard/google/chell/romstage.c @@ -15,36 +15,19 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" #include "spd/spd.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - void mainboard_romstage_entry(struct romstage_params *params) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) google_chromeec_kbbacklight(25); - early_config_gpio(); - /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); |