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authorYidi Lin <yidi.lin@mediatek.com>2020-09-22 19:56:20 +0800
committerHung-Te Lin <hungte@chromium.org>2020-11-18 06:13:03 +0000
commit9ee02095fa1b5c532f758e287401423138687b56 (patch)
tree04ebf5e626718032b75203c35219d84066dda28b /src/mainboard/google
parent9247d128390a70ab8ad5a2eba4ea73dc56a51375 (diff)
downloadcoreboot-9ee02095fa1b5c532f758e287401423138687b56.tar.xz
mb/google/asurada: Implement board-specific regulator controls
Currently, five regulator controls are implemented for DRAM calibration and DVFS feature. The regulators for VCORE and VM18 are controlled by MT6359. The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360 via EC. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/asurada/Makefile.inc1
-rw-r--r--src/mainboard/google/asurada/regulator.c92
2 files changed, 93 insertions, 0 deletions
diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc
index 02fb8300e0..87582b7fbd 100644
--- a/src/mainboard/google/asurada/Makefile.inc
+++ b/src/mainboard/google/asurada/Makefile.inc
@@ -11,6 +11,7 @@ verstage-y += reset.c
romstage-y += memlayout.ld
romstage-y += boardid.c
romstage-y += chromeos.c
+romstage-y += regulator.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
diff --git a/src/mainboard/google/asurada/regulator.c b/src/mainboard/google/asurada/regulator.c
new file mode 100644
index 0000000000..b06388dc66
--- /dev/null
+++ b/src/mainboard/google/asurada/regulator.c
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/mt6359p.h>
+#include <soc/mt6360.h>
+#include <soc/regulator.h>
+
+static int get_mt6360_regulator_id(enum mtk_regulator regulator)
+{
+ switch (regulator) {
+ case MTK_REGULATOR_VDD2:
+ return MT6360_BUCK1;
+ case MTK_REGULATOR_VDDQ:
+ return MT6360_LDO7;
+ case MTK_REGULATOR_VMDDR:
+ return MT6360_LDO6;
+ default:
+ break;
+ }
+
+ return -1;
+}
+
+static int get_mt6359p_regulator_id(enum mtk_regulator regulator)
+{
+ switch (regulator) {
+ case MTK_REGULATOR_VCORE:
+ return MT6359P_GPU11;
+ default:
+ break;
+ }
+
+ return -1;
+}
+
+void mainboard_set_regulator_vol(enum mtk_regulator regulator,
+ uint32_t voltage_uv)
+{
+ /*
+ * Handle the regulator that does not have a regulator ID
+ * in its underlying implementation.
+ */
+ if (regulator == MTK_REGULATOR_VDD1) {
+ mt6359p_set_vm18_voltage(voltage_uv);
+ return;
+ }
+
+ int id;
+
+ id = get_mt6360_regulator_id(regulator);
+ if (id >= 0) {
+ uint32_t voltage_mv = voltage_uv / 1000;
+ google_chromeec_regulator_set_voltage(id, voltage_mv, voltage_mv);
+ return;
+ }
+
+ id = get_mt6359p_regulator_id(regulator);
+ if (id >= 0) {
+ mt6359p_buck_set_voltage(id, voltage_uv);
+ return;
+ }
+
+ printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator);
+}
+
+uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator)
+{
+ /*
+ * Handle the regulator that does not have a regulator ID
+ * in its underlying implementation.
+ */
+ if (regulator == MTK_REGULATOR_VDD1)
+ return mt6359p_get_vm18_voltage();
+
+ int id;
+
+ id = get_mt6360_regulator_id(regulator);
+ if (id >= 0) {
+ uint32_t voltage_mv = 0;
+ google_chromeec_regulator_get_voltage(id, &voltage_mv);
+ return voltage_mv * 1000;
+ }
+
+ id = get_mt6359p_regulator_id(regulator);
+ if (id >= 0)
+ return mt6359p_buck_get_voltage(id);
+
+ printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator);
+
+ return 0;
+}