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authorSubrata Banik <subrata.banik@intel.com>2018-12-31 16:23:44 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-01-03 04:31:35 +0000
commite2c653e049d0c4db6c2712658eaa5838dac73ee9 (patch)
tree71059f86a90fc73adf681916beb99a48281a42af /src/mainboard/google
parent12992f62c0391b2711f9f125e5f1123e08807836 (diff)
downloadcoreboot-e2c653e049d0c4db6c2712658eaa5838dac73ee9.tar.xz
mb/google/hatch: Make WP_RO range align with winbond specification
This patch ensures to make memory protected range between 01C00000h - 01FFFFFFh as per winbond spi datasheet https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf section 7.1.15 BUG=none BRANCH=none TEST=build for hatch. Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30552 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/hatch/chromeos.fmd10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
index 53ba33804f..25d579b66d 100644
--- a/src/mainboard/google/hatch/chromeos.fmd
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -27,15 +27,17 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
- RW_LEGACY(CBFS)@0x5d0000 0x200000
- WP_RO@0x7d0000 0x430000 {
+ RW_LEGACY(CBFS)@0x5d0000 0x230000
+ # Make WP_RO region align with SPI vendor
+ # memory protected range specification.
+ WP_RO@0x800000 0x400000 {
RO_VPD@0x0 0x4000
- RO_SECTION@0x4000 0x42c000 {
+ RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x33c000
+ COREBOOT(CBFS)@0xf0000 0x30c000
}
}
}