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authorV Sowmya <v.sowmya@intel.com>2018-12-27 14:53:14 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-12-31 04:22:18 +0000
commit3f3d6b3e270ad457526ae56babb01e2101d407a5 (patch)
tree03e088a788efbeaf6a3e85732d7d552db35badd1 /src/mainboard/google
parent5c1f17807571f5a00be94c0eb69b59ea4fea15b3 (diff)
downloadcoreboot-3f3d6b3e270ad457526ae56babb01e2101d407a5.tar.xz
mb/google/hatch: Add the USB port configuration
This patch adds the configurations for, * USB 2.0 ports. * USB 3.0 ports. * Enables USB xHCI controller. * GPIO config for USB2_OC2 and USB2_OC3. * Add the ACPI objects to configure USB ports. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30457 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb94
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c4
2 files changed, 97 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index a42f93dce2..22a847ae1f 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -45,6 +45,23 @@ chip soc/intel/cannonlake
register "SataPortsDevSlp[1]" = "1"
register "satapwroptimize" = "1"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
+ register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
+ register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # BT
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
+ register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY"
device domain 0 on
device pci 00.0 on end # Host Bridge
@@ -53,7 +70,82 @@ chip soc/intel/cannonlake
device pci 12.0 off end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
- device pci 14.0 off end # USB xHCI
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port 1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port 1""
+ register "type" = "UPC_TYPE_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-C Port""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(1, 1)"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-C Port 1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "group" = "ACPI_PLD_GROUP(2, 1)"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Left Type-A Port""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(1, 2)"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Right Type-A Port 1""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "group" = "ACPI_PLD_GROUP(2, 2)"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""WWAN""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 3.4 on end
+ end
+ end
+ end
+ end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.5 off end # SDCard
device pci 15.0 on
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index fe7d1d89d8..eca5f47c92 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -49,6 +49,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
/* SATA_DEVSLP1 */
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ /* USB_C_OC_OD USB_OC2*/
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+ /* USB_A_OC_OD USB_OC3*/
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* PCH_MEM_STRAP0 */
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
/* PCH_MEM_STRAP1 */