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authorAndrew Bresticker <abrestic@chromium.org>2013-12-18 22:41:34 -0800
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-09-22 19:00:19 +0200
commit24d4f7f8defca9c68d4a96ba5cbedf5b01ca6e53 (patch)
treea38ef152b5381a72d68cef5e1860daffd1198227 /src/mainboard/google
parentd65e214d666269d0bd20d88ba2bc83349810c668 (diff)
downloadcoreboot-24d4f7f8defca9c68d4a96ba5cbedf5b01ca6e53.tar.xz
tegra124/nyan: memory and display updates
tegra124: use pll_c_out1 as sclk parent Reviewed-on: https://chromium-review.googlesource.com/180865 (cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f) tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8) Squashed 18 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6914 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/nyan/bct/spi.cfg17
-rw-r--r--src/mainboard/google/nyan/mainboard.c17
2 files changed, 27 insertions, 7 deletions
diff --git a/src/mainboard/google/nyan/bct/spi.cfg b/src/mainboard/google/nyan/bct/spi.cfg
index b348ed82f3..7d05363446 100644
--- a/src/mainboard/google/nyan/bct/spi.cfg
+++ b/src/mainboard/google/nyan/bct/spi.cfg
@@ -14,3 +14,20 @@ DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
+DevType[1] = NvBootDevType_Spi;
+DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[1].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0;
+
+DevType[2] = NvBootDevType_Spi;
+DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[2].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0;
+
+DevType[3] = NvBootDevType_Spi;
+DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[3].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index 1229e7485f..6fa8a95bba 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -89,11 +89,11 @@ static void setup_pinmux(void)
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
- PINMUX_PULL_UP |
+ PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
- PINMUX_PULL_UP |
+ PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
@@ -216,9 +216,9 @@ static void setup_kernel_info(void)
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
- writel(0, &mc->mc_vpr_bom);
- writel(0, &mc->mc_vpr_size);
- writel(1, &mc->mc_vpr_ctrl);
+ writel(0, &mc->video_protect_bom);
+ writel(0, &mc->video_protect_size_mb);
+ writel(1, &mc->video_protect_reg_ctrl);
}
static void setup_ec_spi(void)
@@ -243,14 +243,17 @@ static void mainboard_init(device_t dev)
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
+ *
+ * Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either
+ * initialized by BootROM, or in romstage SDRAM initialization.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X,
- CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
- CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
+ CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC |
+ CLK_H_USB3,
CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,