diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-02-08 17:19:10 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-01 20:54:34 +0100 |
| commit | 2a696c07b9cdcd484800596fb850f95260419d11 (patch) | |
| tree | bb922c5bb0cb92fe7e7dc4d15fdf860bae325046 /src/mainboard/google | |
| parent | f4b7f2258405389be43ae0690914df67b83ae163 (diff) | |
| download | coreboot-2a696c07b9cdcd484800596fb850f95260419d11.tar.xz | |
Skylake boards: Enabling HWP (hardware P state control)
This patch provides config options to enable/disable Intel SST
(Speed Shift Technology).
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu/lars, verified HWP driver load successfully.
CQ-DEPEND=CL:313107
Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/326650
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://review.coreboot.org/13843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/chell/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/lars/devicetree.cb | 3 |
3 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index ac3a5c1da2..bb925cebe1 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 894f0e1858..89fcff8ccd 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index cf3649aa4d..50b3e1e8dc 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" |