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authorLijian Zhao <lijian.zhao@intel.com>2019-01-23 13:23:01 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-25 11:21:39 +0000
commit38e40414d250abfdc7213e6dfa11beb8d7082489 (patch)
treeb5c7e016eb3ad56ed5ed9765585486c3701af5ca /src/mainboard/google
parent57aa8b6a2b5d3272e1ea1a0ed69ca2e0ef346291 (diff)
downloadcoreboot-38e40414d250abfdc7213e6dfa11beb8d7082489.tar.xz
mb/google/sarien: Increse BIOS region size to 28MB
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for upcoming payloads. BUG=b:121169122 TEST=Build and boot up fine into OS on sarien and arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237 Reviewed-on: https://review.coreboot.org/c/31054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/sarien/chromeos.fmd20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd
index ba42a6f622..2408a30403 100644
--- a/src/mainboard/google/sarien/chromeos.fmd
+++ b/src/mainboard/google/sarien/chromeos.fmd
@@ -1,27 +1,27 @@
FLASH@0xfe000000 0x2000000 {
- SI_ALL@0x0 0x1000000 {
+ SI_ALL@0x0 0x400000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000
SI_GBE@0x101000 0x2000
- SI_ME@0x103000 0xef9000
- SI_PDR@0xffc000 0x4000
+ SI_ME@0x103000 0x2f9000
+ SI_PDR@0x3fc000 0x4000
}
- SI_BIOS@0x1000000 0x1000000 {
- RW_DIAG@0x0 0x6d0000 {
+ SI_BIOS@0x400000 0x1c00000 {
+ RW_DIAG@0x0 0x12d0000 {
DIAG_NVRAM@0x0 0x10000
- RW_LEGACY(CBFS)@0x10000 0x6c0000
+ RW_LEGACY(CBFS)@0x10000 0x12c0000
}
- RW_SECTION_A@0x6d0000 0x280000 {
+ RW_SECTION_A@0x12d0000 0x280000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x26ffc0
RW_FWID_A@0x27ffc0 0x40
}
- RW_SECTION_B@0x950000 0x280000 {
+ RW_SECTION_B@0x1550000 0x280000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x26ffc0
RW_FWID_B@0x27ffc0 0x40
}
- RW_MISC@0xbd0000 0x30000 {
+ RW_MISC@0x17d0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
@@ -34,7 +34,7 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
- WP_RO@0xc00000 0x400000 {
+ WP_RO@0x1800000 0x400000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {