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authorRonald G. Minnich <rminnich@gmail.com>2013-02-20 15:46:46 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-02-25 18:50:00 +0100
commit3faa2c77ed9103839002d1092424676790f07017 (patch)
tree9744ab04553e7ed3be1714fd4eb765d582a950c1 /src/mainboard/google
parent5f20b3522212f58b5e6858ff7028fb5a8e0879f5 (diff)
downloadcoreboot-3faa2c77ed9103839002d1092424676790f07017.tar.xz
google/snow: enable GPIO entries and CHROMEOS in building
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/snow/Kconfig2
-rw-r--r--src/mainboard/google/snow/Makefile.inc1
-rw-r--r--src/mainboard/google/snow/chromeos.c98
3 files changed, 100 insertions, 1 deletions
diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig
index bee987d7b7..6face944bb 100644
--- a/src/mainboard/google/snow/Kconfig
+++ b/src/mainboard/google/snow/Kconfig
@@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select DRIVER_MAXIM_MAX77686
# select HAVE_ACPI_TABLES
# select MMCONF_SUPPORT
-# select CHROMEOS
+ select CHROMEOS
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc
index b56a1a42cf..668e3b72ba 100644
--- a/src/mainboard/google/snow/Makefile.inc
+++ b/src/mainboard/google/snow/Makefile.inc
@@ -23,6 +23,7 @@ romstage-y += romstage.c
# ramstage-y += ec.c
ramstage-y += ramstage.c
+ramstage-y += chromeos.c
# romstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c
new file mode 100644
index 0000000000..5f8e6312d5
--- /dev/null
+++ b/src/mainboard/google/snow/chromeos.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+
+#include <device/device.h>
+
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+#define WP_GPIO 6
+#define DEVMODE_GPIO 54
+#define FORCE_RECOVERY_MODE 0
+#define FORCE_DEVELOPER_MODE 0
+
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT 4
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ /* Write Protect: virtual GPIO active Low */
+ gpios->gpios[0].port = -1;
+ gpios->gpios[0].polarity = ACTIVE_LOW;
+ gpios->gpios[0].value = 1;
+ strncpy((char *)gpios->gpios[0].name,"write protect",
+ GPIO_MAX_NAME_LENGTH);
+
+ /* Recovery: virtual GPIO active high */
+ gpios->gpios[1].port = -1;
+ gpios->gpios[1].polarity = ACTIVE_HIGH;
+ gpios->gpios[1].value = 0;
+ strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[2].port = -1;
+ gpios->gpios[2].polarity = ACTIVE_HIGH;
+ gpios->gpios[2].value = 1;
+ strncpy((char *)gpios->gpios[2].name,"developer",
+ GPIO_MAX_NAME_LENGTH);
+
+ /* Was VGA Option ROM loaded? */
+ gpios->gpios[3].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[3].polarity = ACTIVE_HIGH;
+ gpios->gpios[3].value = 0;
+ strncpy((char *)gpios->gpios[3].name,"oprom", GPIO_MAX_NAME_LENGTH);
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", GPIO_COUNT, gpios->size);
+
+}
+
+int get_developer_mode_switch(void)
+{
+ int dev_mode = 0;
+
+ printk(BIOS_DEBUG,"FORCING DEVELOPER MODE.\n");
+
+ dev_mode = 1;
+ printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO,
+ dev_mode);
+
+ return dev_mode;
+}
+
+int get_recovery_mode_switch(void)
+{
+ int ec_rec_mode = 0;
+
+ return ec_rec_mode;
+}
+
+int get_recovery_mode_from_vbnv(void)
+{
+ return 1;
+}