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authorAamir Bohra <aamir.bohra@intel.com>2020-05-19 20:21:36 +0530
committerKarthik Ramasubramanian <kramasub@google.com>2020-06-02 03:25:31 +0000
commit3fd5a1bbbb7a112544975045a0c4ac1f3ea82202 (patch)
treed464d93f04f9adfb1a9b836c617f102a506003ce /src/mainboard/google
parent87e36c442e33388493f259bfa14db460a4f02753 (diff)
downloadcoreboot-3fd5a1bbbb7a112544975045a0c4ac1f3ea82202.tar.xz
mb/google/dedede: Enable coreboot lock down config
TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index fc4397689e..72ce7c1821 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -140,6 +140,7 @@ chip soc/intel/jasperlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
@@ -151,6 +152,7 @@ chip soc/intel/jasperlake
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,