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authorVladimir Serbinenko <phcoder@gmail.com>2016-02-10 02:51:48 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2016-02-12 09:06:39 +0100
commit4a84e472112b7f646ba326fd2f0f693253905e8d (patch)
tree8cc17c371d9693e1ba49788f2e9bb55c49261c43 /src/mainboard/google
parent0544b31a4986ab286dd3a2c27907a76eee81078d (diff)
downloadcoreboot-4a84e472112b7f646ba326fd2f0f693253905e8d.tar.xz
Fix butterfly usb map.
This was copied from mrc structure despite them having fields in different order. Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13661 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/butterfly/romstage.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 65a294c555..99139e44a9 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -107,21 +107,21 @@ void rcba_config(void)
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
- /* enabled usb oc pin length */
- { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
- { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
- { 1, 0, 0x0040 }, /* P2: Camera (no OC) */
- { 0, 0, 0x0000 }, /* P3: Empty */
- { 0, 0, 0x0000 }, /* P4: Empty */
- { 0, 0, 0x0000 }, /* P5: Empty */
- { 0, 0, 0x0000 }, /* P6: Empty */
- { 0, 0, 0x0000 }, /* P7: Empty */
- { 0, 4, 0x0000 }, /* P8: Empty */
- { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
- { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
- { 0, 4, 0x0000 }, /* P11: Empty */
- { 0, 4, 0x0000 }, /* P12: Empty */
- { 0, 4, 0x0000 }, /* P13: Empty */
+ /* enabled power usb oc pin */
+ { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */
+ { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */
+ { 1, 0, -1 }, /* P2: Camera (no OC) */
+ { 0, 0, -1 }, /* P3: Empty */
+ { 0, 0, -1 }, /* P4: Empty */
+ { 0, 0, -1 }, /* P5: Empty */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 0, 0, -1 }, /* P8: Empty */
+ { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */
+ { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 0, 0, -1 }, /* P12: Empty */
+ { 0, 0, -1 }, /* P13: Empty */
};
void mainboard_get_spd(spd_raw_data *spd) {