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authorDavid Hendricks <dhendrix@chromium.org>2016-11-17 14:19:51 -0800
committerPatrick Georgi <pgeorgi@google.com>2017-03-07 17:45:53 +0100
commit6d5b2f7057d71d925647590462ac8d88109c462c (patch)
tree9cceab0330e25a1e58f8c4b059b035e9d52314a9 /src/mainboard/google
parent16568c7535c7532b7ee9f1ce2231dabd518921e3 (diff)
downloadcoreboot-6d5b2f7057d71d925647590462ac8d88109c462c.tar.xz
google/veyron_*: Add new Micron and Hynix modules
This adds SDRAM entries for the following modules: - Micron: DDMT52L256M64D2PP-107 - Hynix: H9CCNNNBKTALBR-NUD They are compatible with Samsung K4E8E324EB-EGCF, so this just copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used in the comment near the top. Notes on our "special snowflake" boards: - veyron_danger's RAM ID is hard-coded to zero, so I skipped changes involving the binary first numbering scheme. - Rialto's SDRAM mapping is different, so I padded its SDRAM entries to 24 to match other boards. - veyron_mickey requires different MR3 and ODT settings than other boards due to its unique PCB (chrome-os-partner:43626). BUG=chrome-os-partner:59997 BRANCH=none TEST=Booted new modules on Mickey (see BUG) Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3 Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412328 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com> Original-Tested-by: Jiazi Yang <Tomato_Yang@asus.com> Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6) Original-Reviewed-on: https://chromium-review.googlesource.com/446299 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18518 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/veyron/boardid.c2
-rw-r--r--src/mainboard/google/veyron/sdram_configs.c10
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc78
-rw-r--r--src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc78
-rw-r--r--src/mainboard/google/veyron_mickey/boardid.c2
-rw-r--r--src/mainboard/google/veyron_mickey/sdram_configs.c10
-rw-r--r--src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc78
-rw-r--r--src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc78
-rw-r--r--src/mainboard/google/veyron_rialto/boardid.c2
-rw-r--r--src/mainboard/google/veyron_rialto/sdram_configs.c10
10 files changed, 345 insertions, 3 deletions
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
index a610471b0c..47e946e635 100644
--- a/src/mainboard/google/veyron/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
@@ -38,7 +38,7 @@ uint32_t ram_code(void)
gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+ code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
printk(BIOS_SPEW, "RAM Config: %u.\n", code);
return code;
diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
index 76e4f765d1..04a88c4d1c 100644
--- a/src/mainboard/google/veyron/sdram_configs.c
+++ b/src/mainboard/google/veyron/sdram_configs.c
@@ -37,8 +37,18 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */
+#include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */
+#include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 01Z0 */
};
+_Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!");
+
const struct rk3288_sdram_params *get_sdram_config()
{
u32 ramcode = ram_code();
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc
new file mode 100644
index 0000000000..8e0c37acf2
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc
@@ -0,0 +1,78 @@
+{
+ /* 2 Hynix H9CCNNNBKTALBR-NUD chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x2
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 3,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc
new file mode 100644
index 0000000000..94ee5b18ad
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc
@@ -0,0 +1,78 @@
+{
+ /* 2 Micron DDMT52L256M64D2PP-107 chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x2
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 3,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1,
+},
diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c
index a610471b0c..47e946e635 100644
--- a/src/mainboard/google/veyron_mickey/boardid.c
+++ b/src/mainboard/google/veyron_mickey/boardid.c
@@ -38,7 +38,7 @@ uint32_t ram_code(void)
gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+ code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
printk(BIOS_SPEW, "RAM Config: %u.\n", code);
return code;
diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c
index 76e4f765d1..04a88c4d1c 100644
--- a/src/mainboard/google/veyron_mickey/sdram_configs.c
+++ b/src/mainboard/google/veyron_mickey/sdram_configs.c
@@ -37,8 +37,18 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */
+#include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */
+#include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 01Z0 */
};
+_Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!");
+
const struct rk3288_sdram_params *get_sdram_config()
{
u32 ramcode = ram_code();
diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc
new file mode 100644
index 0000000000..8e0c37acf2
--- /dev/null
+++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc
@@ -0,0 +1,78 @@
+{
+ /* 2 Hynix H9CCNNNBKTALBR-NUD chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x2
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 3,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1,
+},
diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc
new file mode 100644
index 0000000000..94ee5b18ad
--- /dev/null
+++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc
@@ -0,0 +1,78 @@
+{
+ /* 2 Micron DDMT52L256M64D2PP-107 chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x2
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 3,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1,
+},
diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c
index a610471b0c..47e946e635 100644
--- a/src/mainboard/google/veyron_rialto/boardid.c
+++ b/src/mainboard/google/veyron_rialto/boardid.c
@@ -38,7 +38,7 @@ uint32_t ram_code(void)
gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+ code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
printk(BIOS_SPEW, "RAM Config: %u.\n", code);
return code;
diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c
index 0e260c3855..eba7a39c39 100644
--- a/src/mainboard/google/veyron_rialto/sdram_configs.c
+++ b/src/mainboard/google/veyron_rialto/sdram_configs.c
@@ -37,8 +37,18 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 001Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z0 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 01Z0 */
};
+_Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!");
+
const struct rk3288_sdram_params *get_sdram_config()
{
u32 ramcode = ram_code();