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authorLijian Zhao <lijian.zhao@intel.com>2018-10-24 17:10:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-11-05 09:04:32 +0000
commitae4eee17dd77f850fbaf34b28c2e4f908a80f22d (patch)
treef73861467792083c218529edb39fc39be6bd8a2f /src/mainboard/google
parent22e0c560bb565642d52e4e0f8bab000c8d06f0b8 (diff)
downloadcoreboot-ae4eee17dd77f850fbaf34b28c2e4f908a80f22d.tar.xz
soc/intel/cannonlake: Remove depreciated UPD selection
Several FSP silicon init UPD have been moved to memory init stage, modify the coreboot accordingly. The UPDs below are affected: SkipMpInit VtdBaseAddress VtdDisable X2ApicOptOut BUG=N/A TEST=Build pass with FSP revision 7.0.47.50. Change-Id: Ic0416dcd9ea1fe063cdd0c2f27257cd4cb4ba7e8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29260 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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