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authorArthur Heymans <arthur@aheymans.xyz>2018-12-22 16:59:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:57:33 +0000
commite43972474c0eebc478722f7c371a8c68318f24cf (patch)
tree34abf5f2a18cb350fe4871b4e8509c5da4705d37 /src/mainboard/google
parent4d56a0625516ba436903d59d9c0a4a13827d89be (diff)
downloadcoreboot-e43972474c0eebc478722f7c371a8c68318f24cf.tar.xz
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/jecht/Makefile.inc4
-rw-r--r--src/mainboard/google/jecht/bootblock.c31
-rw-r--r--src/mainboard/google/jecht/romstage.c12
3 files changed, 34 insertions, 13 deletions
diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc
index 28a284e759..116792fab7 100644
--- a/src/mainboard/google/jecht/Makefile.inc
+++ b/src/mainboard/google/jecht/Makefile.inc
@@ -24,7 +24,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c
romstage-y += variants/$(VARIANT_DIR)/pei_data.c
ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
-romstage-y += led.c
+bootblock-y += led.c
+
+bootblock-y += bootblock.c
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c
new file mode 100644
index 0000000000..43725cd747
--- /dev/null
+++ b/src/mainboard/google/jecht/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include "onboard.h"
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Early SuperIO setup */
+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
+ ite_kill_watchdog(IT8772F_GPIO_DEV);
+ ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Turn On Power LED */
+ set_power_led(LED_ON);
+}
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index 86888c82f8..4fc2ba0c93 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -39,15 +39,3 @@ void mainboard_post_raminit(struct romstage_params *rp)
if (CONFIG(CHROMEOS))
init_bootmode_straps();
}
-
-void mainboard_pre_console_init(void)
-{
- /* Early SuperIO setup */
- it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
- ite_kill_watchdog(IT8772F_GPIO_DEV);
- ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- /* Turn On Power LED */
- set_power_led(LED_ON);
-
-}