diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-01-07 16:55:31 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-19 16:29:00 +0100 |
| commit | ec19fccf7614ae4405829ac0e71460ff18500ee8 (patch) | |
| tree | d5f1ba2e9c337203d5f25b7a6c403f22a7ac8eb3 /src/mainboard/google | |
| parent | 07651fa3fb8062db4322c64e6faf5643eb96efe7 (diff) | |
| download | coreboot-ec19fccf7614ae4405829ac0e71460ff18500ee8.tar.xz | |
google/glados: Set FSP params for min assertion widths and serirq
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
- Disable Deep S3 to match chell so DeepSx story is consistent
on skylake-y boards.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=emerge-glados coreboot (tested on chell board)
Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1
Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321211
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 35 |
1 files changed, 22 insertions, 13 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 62d2553aa8..03c46f4005 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable" = "1" + register "deep_s3_enable" = "0" register "deep_s5_enable" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" @@ -44,6 +44,12 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "HeciEnabled" = "0" register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ @@ -144,20 +150,23 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2 # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoPci, \ + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoPci, }" + # I2C4 is 1.8V + register "SerialIoI2cVoltage[4]" = "1" + device cpu_cluster 0 on device lapic 0 on end end |