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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2017-01-25 23:06:23 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-01-26 19:43:17 +0100 |
| commit | 011792415963e19dfe84da25cd3ab1f31bd55b34 (patch) | |
| tree | 42894b666310a16a7278d0fe770fdaae26720abc /src/mainboard/google | |
| parent | fe8a01b01aea9aaeae67e5d03c699eedc1fc611f (diff) | |
| download | coreboot-011792415963e19dfe84da25cd3ab1f31bd55b34.tar.xz | |
google/pyro: Add USB2 phy setting override
In order to pass type A USB2 eye diagram,
USB2 port#0/#1 PHY register will need to be overridden.
port#0:
PERPORTPETXISET = 7
PERPORTTXISET = 1
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0
BUG=chrome-os-partner:59491
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/reef/variants/pyro/devicetree.cb | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43e4c3d53c..41086f024e 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -105,6 +105,22 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" + # Override USB2 PER PORT register (PORT 0) + register "usb2eye[0]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 1, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + + # Override USB2 PER PORT register (PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 2, + .Usb20IUsbTxEmphasisEn = 3, + .Usb20PerPortTxPeHalf = 0, + }" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |