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author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-18 10:29:06 +0200 |
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committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-27 22:23:05 +0200 |
commit | 0e90dae584c506b06e7bf3d89064a64db04132bb (patch) | |
tree | 83876d4f6e39e432789c0bcdb6384068bdcd566b /src/mainboard/google | |
parent | 40772a0b5afc7d82a213b005905e2d9e71a6328e (diff) | |
download | coreboot-0e90dae584c506b06e7bf3d89064a64db04132bb.tar.xz |
Move TPM code out of chromeos
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/bolt/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/butterfly/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/falco/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/link/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/link/romstage.c | 11 | ||||
-rw-r--r-- | src/mainboard/google/panther/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/parrot/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/parrot/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/google/peppy/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/rambi/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/samus/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/slippy/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/stout/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/google/stout/romstage.c | 10 |
14 files changed, 24 insertions, 18 deletions
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 2239f70a8d..74e1edda5f 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 7472c0668e..b1a64eebad 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index a8faaab3a6..5b97259217 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 316434fbb8..0f709255d2 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index ca8c2bd5ec..b345d5ec3e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -41,9 +41,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -246,8 +244,9 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } + timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 31062edac2..37a8548f0a 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 07405c6098..9cf390ac79 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index d0fab67edb..a947c48666 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #include <cbfs.h> +#include <tpm.h> #include "ec/compal/ene932/ec.h" static void pch_enable_lpc(void) @@ -197,8 +195,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index d6a208bcbe..2c1560aad4 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4c9e89144c..1130d11096 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select ALWAYS_LOAD_OPROM select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index f655b2969b..06317e9468 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index fd4cb2f588..cfbce5e4a3 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index ec03d8761e..eca83da637 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index ee6ca4f520..31b61e2d72 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -40,9 +40,7 @@ #include <halt.h> #include "gpio.h" #include <bootmode.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -251,8 +249,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } |