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| author | Lin Huang <hl@rock-chips.com> | 2016-04-08 18:56:20 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-18 20:23:18 +0200 |
| commit | 2f7ed8d775153db69d19c77cc79db9b0bb136c70 (patch) | |
| tree | 774f21bf49a9f5486c9242e9124d1db48e9eaf04 /src/mainboard/google | |
| parent | 95b7a6c6db47bd493a11fa14aa949ddb6788e8db (diff) | |
| download | coreboot-2f7ed8d775153db69d19c77cc79db9b0bb136c70.tar.xz | |
rockchip: rk3399: configure emmc clk
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz,
that is GPLL(594MHz) divided by 3.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard
TEST=LoadKernel faster, more than twice as I measured manually.
Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2
Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339152
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14855
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/gru/mainboard.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 4a5ed4f687..6d2b4f4759 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -20,6 +20,20 @@ #include <soc/clock.h> #include <soc/grf.h> +static void configure_emmc(void) +{ + /* Host controller does not support programmable clock generator. + * If we don't do this setting, when we use phy to control the + * emmc clock(when clock exceed 50MHz), it will get wrong clock. + * + * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register. + * Please search "_CON11[7:0]" to locate register description. + */ + write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0)); + + rkclk_configure_emmc(); +} + static void configure_sdmmc(void) { gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */ @@ -72,6 +86,7 @@ static void configure_sdmmc(void) static void mainboard_init(device_t dev) { configure_sdmmc(); + configure_emmc(); } static void mainboard_enable(device_t dev) |