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author | Amanda Huang <amanda_hwang@compal.corp-partner.google.com> | 2020-07-28 12:25:35 +0800 |
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committer | Paul Fagerburg <pfagerburg@chromium.org> | 2020-08-06 19:43:44 +0000 |
commit | 3d813cbede650a89a519d5896652328e4ecf88c6 (patch) | |
tree | dd51b43e361b5eef1d29367e602d212b331d082b /src/mainboard/google | |
parent | 79dba4aadc6acbb9c28274109d242fdccdf3db8a (diff) | |
download | coreboot-3d813cbede650a89a519d5896652328e4ecf88c6.tar.xz |
mb/google/volteer/var/halvor: Update dq/dqs mappings
Update dq/dqs mappings based on halvor schematics.
BUG=b:162892573
BRANCH=none
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43988
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r-- | src/mainboard/google/volteer/variants/halvor/Makefile.inc | 2 | ||||
-rw-r--r-- | src/mainboard/google/volteer/variants/halvor/memory.c | 60 |
2 files changed, 62 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db5ec..343c7dbb95 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +romstage-y += memory.c + bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000000..754c7a00c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14, }, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &halvor_memcfg; +} |