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| author | David Hendricks <dhendrix@chromium.org> | 2013-02-12 15:37:12 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-14 07:03:55 +0100 |
| commit | a86e4ba8bdc7fd45ab76697d32d4e95cf3116700 (patch) | |
| tree | 50746a022b70fc83d948c4c07c9e017dae45ef17 /src/mainboard/google | |
| parent | 2d0b55bd6bfc2985950224dbca29668cc1aa7eba (diff) | |
| download | coreboot-a86e4ba8bdc7fd45ab76697d32d4e95cf3116700.tar.xz | |
snow: Set up MMU after DRAM is working
This was omitted earlier while we were debugging DRAM code (0a5bc7f).
It was likely broken due to inconsistent units earlier on. Now that
things are cleaned up and working, let's add it back in.
Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2379
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/snow/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 53072d1efb..9891011fe4 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -82,6 +82,8 @@ void main(void) while(1); } + mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); |