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authorKenji Chen <kenji.chen@intel.com>2015-11-16 17:08:32 +0800
committerMartin Roth <martinroth@google.com>2016-01-28 20:41:14 +0100
commitb1e4bd0d28bb65474c0a954374124f21cac05972 (patch)
treedbc1dcb92637367a72a7ee47b0247457d1cea1b6 /src/mainboard/google
parentc4153c1b15fa88796ce3bcccb49e3537c9e65ff3 (diff)
downloadcoreboot-b1e4bd0d28bb65474c0a954374124f21cac05972.tar.xz
Braswell: Separate L1 Sub State init procedure for boards.
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/cyan/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index c5a1346979..5eb0815435 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM
select SOC_INTEL_BRASWELL
select HAVE_ACPI_RESUME
+ select PCIEXP_L1_SUB_STATE
config CHROMEOS
select LID_SWITCH