diff options
| author | Evan Green <evgreen@chromium.org> | 2019-05-21 15:39:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-23 09:02:48 +0000 |
| commit | c72dc05acc12c65614079bd0de25809b80456141 (patch) | |
| tree | fbbb9988a54fd8e4200aae00c4be0e8d9d5f907a /src/mainboard/google | |
| parent | 298afb3140fa8f092b356ec89d8be2f5a36b530f (diff) | |
| download | coreboot-c72dc05acc12c65614079bd0de25809b80456141.tar.xz | |
mb/google/hatch/variants: Fix DPTF sensor IDs
There are indeed two temperature sensors hooked up to the EC, but they
are indexed as 0 and 1, not 1 and 2.
BUG=b:132999028
TEST=Boot hatch with hardened EC, observe no more index overflows
Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index 1384ccfeb7..ff7db49334 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -21,7 +21,7 @@ #define DPTF_CPU_ACTIVE_AC3 80 #define DPTF_CPU_ACTIVE_AC4 75 -#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 @@ -31,7 +31,7 @@ #define DPTF_TSR0_ACTIVE_AC3 42 #define DPTF_TSR0_ACTIVE_AC4 39 -#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 |