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| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-01-09 20:41:22 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2019-01-10 08:46:08 +0000 |
| commit | cda27c2492929fb4bb734211d9dc3a85202ec1e4 (patch) | |
| tree | a04e0d4f85e402992695c1a6075a71d3d78ea28f /src/mainboard/google | |
| parent | ec558682fc11a985eb1b02b400a86ea9de407796 (diff) | |
| download | coreboot-cda27c2492929fb4bb734211d9dc3a85202ec1e4.tar.xz | |
mb/google/hatch: enable CPU cluster device
Change-Id: I28c67fbdf2b4f371c4b533b64cad2c4376ca2bd2
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30785
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 402a97e90a..ca045076bd 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -74,6 +74,10 @@ chip soc/intel/cannonlake # ClkReq-to-ClkSrc mapping for CLK SRC 1 register "PcieClkSrcClkReq[1]" = "1" + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |