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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-11-01 02:01:02 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-04 11:33:23 +0000 |
| commit | 1845fc89476df67c5981cb2d67ddb11d271154bb (patch) | |
| tree | b7af2168ea8bd5e57cf450a6c1b49e57462cb72d /src/mainboard/google | |
| parent | e979442cd6c98b9f757d672dcd363a385182397d (diff) | |
| download | coreboot-1845fc89476df67c5981cb2d67ddb11d271154bb.tar.xz | |
mb/google/drallion: fix GPP_E16 glitch when enter S5
Set GPP_E16 reset to DEEP.
BUG=b:143057255
BRANCH=N/A
TEST=Measure GPP_E16 from S0 to S5 has no glitch
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index e699e4b165..697d3056a6 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -154,7 +154,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* HDMI_PD# */ +/* DDPE_HPD3 */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* HDMI_PD# */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), |