diff options
| author | Rajat Jain <rajatja@google.com> | 2017-07-20 19:31:01 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-07-23 04:01:04 +0000 |
| commit | 2671afcbbcf5bbf3391011b25509eadb4f5a16b7 (patch) | |
| tree | 163f903f3300487972a64e02cbbc74d6fda7ea46 /src/mainboard/google | |
| parent | 9aa45e6952ec42f8a3ccc2bfaa15a782ad81aeb6 (diff) | |
| download | coreboot-2671afcbbcf5bbf3391011b25509eadb4f5a16b7.tar.xz | |
mainboard/google/{poppy,soraka}: Enable S0ix
Enable S0ix for poppy and soraka in their device trees respectively.
BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).
Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 789b21a7fc..cabf3dea9a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -24,6 +24,9 @@ chip soc/intel/skylake # Enable DPTF register "dptf_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 9b8a18c2b0..3de9854bdc 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -24,6 +24,9 @@ chip soc/intel/skylake # Enable DPTF register "dptf_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" |