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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-02-28 16:25:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 21:28:56 +0000 |
| commit | 4ebe6dff1a9b2643e739371d3399f25a2c0e68a2 (patch) | |
| tree | ff30b8f90e8e5687de1495a66d6c343348bb6b0d /src/mainboard/google | |
| parent | c83c5af3ae0e52c54ce4cc42134697d2d3ecfc60 (diff) | |
| download | coreboot-4ebe6dff1a9b2643e739371d3399f25a2c0e68a2.tar.xz | |
mb/google/dedede: Add PCIe Root Port Configuration
Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d5f58bae3e..0efb76dfe0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -76,6 +76,31 @@ chip soc/intel/tigerlake [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + # PCIE Root Port Configuration + register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[1]" = "0" + register "PcieRpEnable[2]" = "0" + register "PcieRpEnable[3]" = "0" + register "PcieRpEnable[4]" = "0" + register "PcieRpEnable[5]" = "0" + register "PcieRpEnable[6]" = "0" + register "PcieRpEnable[7]" = "0" + + register "PcieClkSrcUsage[0]" = "0xff" + register "PcieClkSrcUsage[1]" = "0xff" + register "PcieClkSrcUsage[2]" = "0xff" + register "PcieClkSrcUsage[3]" = "0xff" + register "PcieClkSrcUsage[4]" = "0xff" + register "PcieClkSrcUsage[5]" = "0xff" + + # PCIE Clock Request to Clock Source Mapping + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" |