diff options
author | Iru Cai <mytbk920423@gmail.com> | 2017-07-07 13:32:40 +0800 |
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committer | Martin Roth <martinroth@google.com> | 2017-08-18 15:31:21 +0000 |
commit | 728d488ab39c44721300588f81626263e538cae5 (patch) | |
tree | ba3ad4dc88670b7edcef09e015871352a766a9ce /src/mainboard/hp/8460p/devicetree.cb | |
parent | 6f08ef9bdaec2a81cd6d70192aa37bda2ace6640 (diff) | |
download | coreboot-728d488ab39c44721300588f81626263e538cae5.tar.xz |
mainboard/hp: Add HP Elitebook 8460p
The code is based on autoport. I'm using a machine with discrete GPU,
and gfx.* in devicetree.cb is from 2760p.
It can be debug with serial port on dock.
Tested:
- CPU and memory: i5-2540M, 4G+0
- Arch Linux (Linux 4.11.7, SeaBIOS payload, with ATOM BIOS extracted
from vendor UEFI firmware)
- USB ports
- SD card reader
- WLAN
- DP display
- S3
Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/hp/8460p/devicetree.cb')
-rw-r--r-- | src/mainboard/hp/8460p/devicetree.cb | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb new file mode 100644 index 0000000000..4b1df4a5ac --- /dev/null +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -0,0 +1,153 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000129" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x161c + end + device pci 01.0 on # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics + subsystemid 0x103c 0x161c + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3b" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" + + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x161c + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x103c 0x161c + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x161c + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x161c + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x161c + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x161c + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x161c + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x161c + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x161c + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 + subsystemid 0x103c 0x161c + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x161c + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x161c + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end # kbc1126 + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off # Com2 + end + end #chip superio/smsc/lpc47n217 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x161c + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end |