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authorIru Cai <mytbk920423@gmail.com>2018-01-22 14:43:50 +0800
committerMartin Roth <martinroth@google.com>2018-03-02 15:20:10 +0000
commitd2517af6f9fe6d9ecb18d95ae9dd0388f8140c77 (patch)
tree344cb3d5d44f31e03a8564dde077d350af43ce54 /src/mainboard/hp/8470p
parent45cc2ba882f72503d56d94d3e7ae40b27fc9b18b (diff)
downloadcoreboot-d2517af6f9fe6d9ecb18d95ae9dd0388f8140c77.tar.xz
mb/hp: Enable additional ports at WWAN slot for Elitebooks
2760p: enable PCIe 8470p: enable mSATA 8460p: enable PCIe, also add comments according to circuit diagram 2570p: comment for some USB ports Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/hp/8470p')
-rw-r--r--src/mainboard/hp/8470p/devicetree.cb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb
index b7254bb38d..9d6fe3ff23 100644
--- a/src/mainboard/hp/8470p/devicetree.cb
+++ b/src/mainboard/hp/8470p/devicetree.cb
@@ -68,7 +68,8 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
- register "sata_port_map" = "0x3b"
+ # HDD(0), ODD(1), mSATA(2), eSATA(4)
+ register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"