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| author | Idwer Vollering <vidwer@gmail.com> | 2020-01-05 01:44:25 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-09 16:03:07 +0000 |
| commit | c2ce370f30b60daf60e23182cf01eb898d35fbbd (patch) | |
| tree | 7b4fc0f6682a74264c617a26010a8bb1be215a4c /src/mainboard/hp/abm | |
| parent | 7c0711092371a7e92c7b37d252ac4a74992dac87 (diff) | |
| download | coreboot-c2ce370f30b60daf60e23182cf01eb898d35fbbd.tar.xz | |
src/mainboard: remove MMIO macros
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/hp/abm')
| -rw-r--r-- | src/mainboard/hp/abm/romstage.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index d7322c9eee..079bd7b786 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <amdblocks/acpimmio.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> @@ -25,8 +26,7 @@ void board_BeforeAgesa(struct sysinfo *cb) { - u32 *addr32; - u32 t32; + u32 reg32; /* For serial port option, plug-in card on LPC. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -47,17 +47,15 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ - addr32 = (u32 *)0xfed80e28; - t32 = *addr32; - t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - t32 |= 0x00010000; // Set bit 16 for 25MHz - *addr32 = t32; + reg32 = misc_read32(0x28); + reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + reg32 |= 0x00010000; // Set bit 16 for 25MHz + misc_write32(0x28, reg32); /* Enable Auxiliary OSCOUT1/OSCOUT2 */ - addr32 = (u32 *)0xfed80e40; - t32 = *addr32; - t32 &= 0xffffff7b; // clear 2, 7 - *addr32 = t32; + reg32 = misc_read32(0x40; + reg32 &= 0xffffff7b; // clear 2, 7 + misc_write32(0x40, reg32); nct5104d_enable_uartd(SERIAL_DEV); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |