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| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-21 16:30:00 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-05-26 11:47:19 +0000 |
| commit | ec6e03e4d8b75af84bbc5698912202edf43ba20a (patch) | |
| tree | e24fc485418c95301ef6225ba248323be509eb4a /src/mainboard/hp/abm | |
| parent | 64829161111ea833453df8479d1bada1f91ee511 (diff) | |
| download | coreboot-ec6e03e4d8b75af84bbc5698912202edf43ba20a.tar.xz | |
AGESA f14/f15tn/f16kb: Deduplicate RAM settings
On AGESA f14/f15tn, various RAM-related options were defined in an enum.
However, the preprocessor mess can't compare enum values. To make AGESA
build, each board redefined them as macros, shadowing the enum elements.
Clean this up by replacing the enums with macros in AGESA headers, and
delete the now-redundant redefinitions from all the mainboards.
Note that AGESA f16kb already uses macros, but each mainboard still had
commented-out definitions. Remove them as well, as they are unnecessary.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/hp/abm')
| -rw-r--r-- | src/mainboard/hp/abm/buildOpts.c | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 8efd0a2b8c..12974844ec 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -210,33 +210,6 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -/* MEMORY_BUS_SPEED */ -//#define DDR400_FREQUENCY 200 ///< DDR 400 -//#define DDR533_FREQUENCY 266 ///< DDR 533 -//#define DDR667_FREQUENCY 333 ///< DDR 667 -//#define DDR800_FREQUENCY 400 ///< DDR 800 -//#define DDR1066_FREQUENCY 533 ///< DDR 1066 -//#define DDR1333_FREQUENCY 667 ///< DDR 1333 -//#define DDR1600_FREQUENCY 800 ///< DDR 1600 -//#define DDR1866_FREQUENCY 933 ///< DDR 1866 -//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 -//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 -//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 -//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -// -///* QUANDRANK_TYPE */ -//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM -// -///* USER_MEMORY_TIMING_MODE */ -//#define TIMING_MODE_AUTO 0 ///< Use best rate possible -//#define TIMING_MODE_LIMITED 1 ///< Set user top limit -//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed -// -///* POWER_DOWN_MODE */ -//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode - /* * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. |