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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-26 22:35:11 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-26 22:35:11 +0000 |
| commit | 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (patch) | |
| tree | b9e14e6c08cdcc52b4fa00cfe730fffa55ae137e /src/mainboard/hp/dl145_g1 | |
| parent | df323fcefd6020f8f418a13d65a075d282eed3de (diff) | |
| download | coreboot-1f7d3c5672ec90f8d71907b1a07c8a87fa461047.tar.xz | |
AMD-8111: Add TINY_BOOTBLOCK support.
Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/hp/dl145_g1')
| -rw-r--r-- | src/mainboard/hp/dl145_g1/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 5352ccc48c..a920cc840f 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -88,7 +88,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #define RC0 ((1<<1)<<8) // Not sure about these values @@ -115,7 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) |