src/mainboard/getac - kontron: Add space around operators

Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 26 insertions, 26 deletions

diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c
index c85f380bf0..47e0a3ab8c 100644
--- a/src/mainboard/hp/dl145_g1/acpi_tables.c
+++ b/src/mainboard/hp/dl145_g1/acpi_tables.c
@@ -25,7 +25,7 @@
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-	unsigned int gsi_base=0x18;
+	unsigned int gsi_base = 0x18;
 
 	struct mb_sysconf_t *m;
 
@@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 		int i;
 		int j = 0;
 
-		for(i=1; i< sysconf.hc_possible_num; i++) {
+		for(i = 1; i< sysconf.hc_possible_num; i++) {
 			unsigned d = 0;
 			if(!(sysconf.pci1234[i] & 0x1) ) continue;
 			// 8131 need to use +4
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index fb0c62b18e..877cb5b03b 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -24,13 +24,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	memcpy(header->oem_id,OEM_ID,6);
 	memcpy(header->oem_table_id,"COREBOOT",8);
 	memcpy(header->asl_compiler_id,ASLC,4);
-	header->asl_compiler_revision=0;
+	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	// 3=Workstation,4=Enterprise Server, 7=Performance Server
-	fadt->preferred_pm_profile=0x04;
-	fadt->sci_int=9;
+	// 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+	fadt->preferred_pm_profile = 0x04;
+	fadt->sci_int = 9;
 
 	// disable system management mode by setting to 0:
 	fadt->smi_cmd = 0;//pm_base+0x2f;
@@ -59,8 +59,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	fadt->cst_cnt    = 0xe3;
 	fadt->p_lvl2_lat =  101; // > 100 means system doesnt support C2 state
 	fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
-	fadt->flush_size = 0;    // ignored if wbindv=1 in flags
-	fadt->flush_stride = 0;  // ignored if wbindv=1 in flags
+	fadt->flush_size = 0;    // ignored if wbindv = 1 in flags
+	fadt->flush_stride = 0;  // ignored if wbindv = 1 in flags
 	fadt->duty_offset = 1;
 	fadt->duty_width = 3;    // 0 means duty cycle not supported
 	// _alrm value 0 means RTC alarm feature not supported
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index 9c35814f03..da02095855 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -52,7 +52,7 @@ void get_bus_conf(void)
 	device_t dev;
 	int i;
 
-	if(get_bus_conf_done==1) return; //do it only once
+	if(get_bus_conf_done == 1) return; //do it only once
 
 	get_bus_conf_done = 1;
 
@@ -60,7 +60,7 @@ void get_bus_conf(void)
 	struct mb_sysconf_t *m = sysconf.mb;
 
 	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for(i=0;i<sysconf.hc_possible_num; i++) {
+	for(i = 0; i < sysconf.hc_possible_num; i++) {
 		sysconf.pci1234[i] = pci1234x[i];
 		sysconf.hcdn[i] = hcdnx[i];
 	}
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index 4988ea1691..597acca7e6 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq_info++;
 	slot_num++;
 //pcix bridge
-//      write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+//      write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //      pirq_info++; slot_num++;
 
 	pirq_info++;
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 8b5b428f31..ea0b60c525 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -28,12 +28,12 @@ static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
 		/* Set the memreset low. */
-		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16);
 		/* Ensure the BIOS has control of the memory lines. */
-		outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+		outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 	} else {
 		/* Ensure the CPU has control of the memory lines. */
-		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+		outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 	}
 }
 
@@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 	if (is_cpu_pre_c0()) {
 		udelay(800);
 		/* Set memreset high. */
-		outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+		outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);
 		udelay(90);
 	}
 }
@@ -53,11 +53,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	int ret,i;
 	unsigned device=(ctrl->channel0[0])>>8;
-	/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-	i=2;
+	/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+	i = 2;
 	do {
 		ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-	} while ((ret!=0) && (i-->0));
+	} while ((ret != 0) && (i-->0));
 	smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
 
@@ -65,11 +65,11 @@ static inline void change_i2c_mux(unsigned device)
 {
 	int ret, i;
 	printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
-	i=2;
+	i = 2;
 	do {
 		ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 		printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
-	} while ((ret!=0) && (i-->0));
+	} while ((ret != 0) && (i-->0));
 	ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
 	printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
 }
@@ -91,8 +91,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/fidvid.c"
 #endif
 
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
+#define RC0 ((1 << 1)<<8)
+#define RC1 ((1 << 2)<<8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		{
 		/* Read FIDVID_STATUS */
 			msr_t msr;
-			msr=rdmsr(0xc0010042);
+			msr = rdmsr(0xc0010042);
 			printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 		}
 
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		// show final fid and vid
 		{
 			msr_t msr;
-			msr=rdmsr(0xc0010042);
+			msr = rdmsr(0xc0010042);
 			printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 		}
 
@@ -173,10 +173,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_smbus();
 
 	int i;
-	for(i=0;i<2;i++) {
+	for(i = 0; i < 2; i++) {
 		activate_spd_rom(&sysinfo->ctrl[i]);
 	}
-	for(i=RC0;i<=RC1;i<<=1) {
+	for(i = RC0; i <= RC1; i<<=1) {
 		change_i2c_mux(i);
 	}