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| author | enok71 <enok@lysator.liu.se> | 2011-09-28 16:55:59 +0200 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-10-03 23:17:33 +0200 |
| commit | af90275a41169fa16459ce13b729ab2875199aa1 (patch) | |
| tree | 27ef42b0fc5c1c3065c0f90c8ea9b3bca218cbac /src/mainboard/hp/dl145_g1 | |
| parent | 8eb4273290ea577d06282d350e3fe884145c4288 (diff) | |
| download | coreboot-af90275a41169fa16459ce13b729ab2875199aa1.tar.xz | |
TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.
Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/hp/dl145_g1')
| -rw-r--r-- | src/mainboard/hp/dl145_g1/romstage.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index c3d28546cc..f51b4c4240 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -4,7 +4,6 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> @@ -13,13 +12,11 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -88,7 +85,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" #define RC0 ((1<<1)<<8) // Not sure about these values #define RC1 ((1<<2)<<8) // Not sure about these values @@ -110,12 +106,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - } - if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); |