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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-08 08:22:04 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-08 08:22:04 +0000 |
| commit | d35192544675575276482e5ce65d1b6a6fd9e4a0 (patch) | |
| tree | 6bf1a6e9cd6989ddf2e70ffa8cde40b8239369c4 /src/mainboard/hp/dl145_g3 | |
| parent | 8301d8348a0848d56fdf4dbd76acd6bdcd3fc944 (diff) | |
| download | coreboot-d35192544675575276482e5ce65d1b6a6fd9e4a0.tar.xz | |
Move "select CACHE_AS_RAM" lines from boards into CPU socket.
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
into the socket directories, and remove it from the individual boards.
Do the same for Intel CPUs/sockets where all boards use CAR.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/hp/dl145_g3')
| -rw-r--r-- | src/mainboard/hp/dl145_g3/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index e4c1aa8d3b..8be67520ad 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select CACHE_AS_RAM select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_512 |