diff options
author | Iru Cai <mytbk920423@gmail.com> | 2020-11-09 00:24:58 +0800 |
---|---|---|
committer | Iru Cai <mytbk920423@gmail.com> | 2020-11-14 18:10:49 +0800 |
commit | e5e233e6d9dc12dbccdf07b810869d659954129c (patch) | |
tree | 7f554c61f34ccb1b45011aba6230853f20410a1b /src/mainboard/hp/folio_9480m_bdw/gpio.c | |
parent | 6615c6eaf798556b94ecc44d241222d6b19cd119 (diff) | |
download | coreboot-e5e233e6d9dc12dbccdf07b810869d659954129c.tar.xz |
[HACK] Add soc/broadwell based hp/folio_9480m code
The laptop still boots with this code.
Change-Id: I0d74c59ff8e8f32f49627fb7edc270887ebd5339
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Diffstat (limited to 'src/mainboard/hp/folio_9480m_bdw/gpio.c')
-rw-r--r-- | src/mainboard/hp/folio_9480m_bdw/gpio.c | 108 |
1 files changed, 108 insertions, 0 deletions
diff --git a/src/mainboard/hp/folio_9480m_bdw/gpio.c b/src/mainboard/hp/folio_9480m_bdw/gpio.c new file mode 100644 index 0000000000..d08713cc5d --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +const struct gpio_config mainboard_gpio_config[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = PCH_GPIO_OUT_LOW, + [3] = PCH_GPIO_OUT_HIGH, + [4] = PCH_GPIO_OUT_HIGH, + [5] = PCH_GPIO_OUT_HIGH, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = PCH_GPIO_OUT_HIGH, + [9] = PCH_GPIO_OUT_HIGH, + [10] = PCH_GPIO_OUT_HIGH, + [11] = PCH_GPIO_OUT_HIGH, + [12] = PCH_GPIO_NATIVE, + [13] = PCH_GPIO_OUT_HIGH, + [14] = PCH_GPIO_OUT_HIGH, + [15] = PCH_GPIO_OUT_HIGH, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = PCH_GPIO_OUT_HIGH, + [19] = PCH_GPIO_NATIVE, + [20] = PCH_GPIO_NATIVE, + [21] = PCH_GPIO_NATIVE, + [22] = PCH_GPIO_OUT_HIGH, + [23] = PCH_GPIO_OUT_HIGH, + [24] = PCH_GPIO_OUT_HIGH, + [25] = PCH_GPIO_OUT_HIGH, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = PCH_GPIO_OUT_HIGH, + [29] = PCH_GPIO_OUT_HIGH, + [30] = PCH_GPIO_NATIVE, + [31] = PCH_GPIO_NATIVE, + [32] = PCH_GPIO_NATIVE, + [33] = PCH_GPIO_NATIVE, + [34] = PCH_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = PCH_GPIO_NATIVE, + [38] = PCH_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = PCH_GPIO_OUT_HIGH, + [44] = PCH_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = PCH_GPIO_OUT_HIGH, + [48] = PCH_GPIO_OUT_LOW, + [49] = PCH_GPIO_OUT_HIGH, + [50] = PCH_GPIO_OUT_HIGH, + [51] = PCH_GPIO_OUT_HIGH, + [52] = PCH_GPIO_OUT_HIGH, + [53] = PCH_GPIO_OUT_HIGH, + [54] = PCH_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = PCH_GPIO_OUT_HIGH, + [57] = PCH_GPIO_OUT_LOW, + [58] = PCH_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = PCH_GPIO_OUT_HIGH, + [61] = PCH_GPIO_OUT_LOW, + [62] = PCH_GPIO_NATIVE, + [63] = PCH_GPIO_NATIVE, + [64] = PCH_GPIO_OUT_HIGH, + [65] = PCH_GPIO_OUT_LOW, + [66] = PCH_GPIO_OUT_HIGH, + [67] = PCH_GPIO_OUT_HIGH, + [68] = PCH_GPIO_OUT_HIGH, + [69] = PCH_GPIO_OUT_HIGH, + [70] = PCH_GPIO_OUT_LOW, + [71] = PCH_GPIO_NATIVE, + [72] = PCH_GPIO_NATIVE, + [73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [74] = PCH_GPIO_NATIVE, + [75] = PCH_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = PCH_GPIO_OUT_LOW, + [81] = PCH_GPIO_NATIVE, + [82] = PCH_GPIO_OUT_HIGH, + [83] = PCH_GPIO_OUT_HIGH, + [84] = PCH_GPIO_OUT_HIGH, + [85] = PCH_GPIO_OUT_HIGH, + [86] = PCH_GPIO_OUT_HIGH, + [87] = PCH_GPIO_OUT_HIGH, + [88] = PCH_GPIO_OUT_HIGH, + [89] = PCH_GPIO_OUT_HIGH, + [90] = PCH_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = PCH_GPIO_OUT_HIGH, + PCH_GPIO_END +}; |